PART 3 (sections 5-7)
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| Applicable Levels: | 2, 3, 4 (multi-chip embedded) |
| Effective Dates: | 2/25/97- |
| Last Modified: | |
| Relevant Assertions: | AS05.09 |
| Relevant Test Requirements: | TE05.09.01 |
| Relevant Vendor Requirements: | VE05.09.01 |
| Applicable Levels: | 2, 3, 4 (multi-chip standalone and embedded) |
| Effective Dates: | 2/25/97- |
| Last Modified: | |
| Relevant Assertions: | AS05.09, AS05.19, AS02.02 |
| Relevant Test Requirements: | TE05.09.01, TE05.19.01, TE02.02.01-.04 |
| Relevant Vendor Requirements: | VE05.09.01, VE05.19.01, VE02.02.01-.04 |
The standard defines a port ("a functional unit of a cryptographic module through which data or signals can enter or exit the module"[Section 2.1]), and makes a distinction between ports and covers ("Documentation shall include a complete specification of the interfaces of a cryptographic module, including any physical or logical ports, physical covers or doors..."[Section 4.2]). At level 2 and above, there are no requirements or tests for tamper evidence other than on removable covers and doors. Thus, there are no requirements for tamper evidence on the various ports listed above (e.g., there does not have to be a tamper evident seal on the keyboard jack where it plugs into the keyboard port, etc.)
| Applicable Levels: | 2, 3, 4 (multi-chip embedded) |
| Effective Dates: | 2/25/97- |
| Last Modified: | |
| Relevant Assertions: | related to AS05.09 |
| Relevant Test Requirements: | |
| Relevant Vendor Requirements: |
Therefore, it may be desirable for the vendor or customer to use tamper evident measures (e.g., cover locks, tamper evident seals, etc.) on the larger embodiment that contains the embedded cryptomodule. However, this lies outside the scope of this standard.
| Applicable Levels: | 3, 4 |
| Effective Dates: | 2/25/97- |
| Last Modified: | |
| Relevant Assertions: | AS05.03, AS05.09, AS05.19 |
| Relevant Test Requirements: | TE05.03.01, TE05.09.01, TE05.19.01 |
| Relevant Vendor Requirements: | VE05.03.01, VE05.09.01, VE05.19.01 |
Tamper evidence and tamper detection/response are not necessarily mutually exclusive. The former warns the valid cryptomodule user that a tamper attempt has occurred, whether it has been successful or not, while the latter protects the cryptomodule from such tamper attempts. In addition, there may be cases where a failure in a module may cause it to be zeroized or disabled (e.g., a blown power supply). There may be cases where keys are zeroized, and without tamper evidence features, there would be no indication that tampering had occurred. The user is left to guess whether zeroization occurred because of tampering or some "natural" failure of the module. Awareness of such tampering would necessitate a more drastic course of action rather than just a simple maintenance procedure, which might be the response if the module simply indicates that keys were zeroized.
The standard and DTR are clear in the area of physical security, in that to meet a particular level, all requirements from lower levels must also be met for a particular type of implementation (e.g., single chip, multi-chip embedded, and multi-chip standalone).
| Applicable Levels: | 2 (multi-chip standalone) |
| Effective Dates: | 9/16/96- |
| Last Modified: | |
| Relevant Assertions: | AS05.19 |
| Relevant Test Requirements: | TE05.19.01 |
| Relevant Vendor Requirements: | VE05.19.01 |
| Applicable Levels: | 3 |
| Effective Dates: | 2/25/97- |
| Last Modified: | |
| Relevant Assertions: | AS05.10, AS05.20 |
| Relevant Test Requirements: | TE05.10.04, TE05.20.04 |
| Relevant Vendor Requirements: | VE05.10.01, VE05.20.01 |
VE05.20.01 states that "the circuitry shall be operational whenever plaintext cryptographic key, or other unprotected critical security parameters, are contained within the module."; this is done even when the module is not powered up (e.g., circuitry operated using battery power).
| Applicable Levels: | 3, 4 |
| Effective Dates: | 3/21/97- |
| Last Modified: | 11/21/97 |
| Relevant Assertions: | AS05.10, AS05.20 |
| Relevant Test Requirements: | TE05.10.04, TE05.20.04 |
| Relevant Vendor Requirements: | VE05.10.01, VE05.20.01 |
(11/21/97)
The tester must determine if Level 3 physical security requirements are met. If fasteners (e.g., rivets, press-fittings, etc.) are used to hold a cover/enclosure in place, and the fasteners are visible to the tester (clearly delineating a mechanism for removal), then it is acceptable for a tester to drill out these fasteners, in order to test the removal of the cover/enclosure for tamper response. Note that drilling can only be performed on the fasteners, and not on the enclosure itself.
In situations where a tester can disable the tamper response mechanism by "removing" the cover/door (as described above) and inserting a physical probe, then the applicable test is failed. If one can use a probe in this manner before zeroization takes place, then it is very likely that a probe could also be used to obtain plaintext critical security parameters. Assertions AS05.11 and AS05.21 address modules that have ventilation slits, and require that these slits be protected to prevent undetected probing. Likewise, the creation of any type of slit or hole during cover/door partial "removal" should also have a similar type of protection to prevent undetected probing (i.e., this protection is the tamper response mechanism).
(11/21/97)
Note that any existing opening revealed by the removal of a fastener may be probed by a tester.
| Applicable Levels: | ALL |
| Effective Dates: | 2/25/97- |
| Last Modified: | |
| Relevant Assertions: | AS07.02, AS11.14 |
| Relevant Test Requirements: | TE07.02.01-.02, TE11.14.03-.04 |
| Relevant Vendor Requirements: | VE07.02.01, VE11.14.01 |
| Applicable Levels: | 2 |
| Effective Dates: | 7/30/97- |
| Last Modified: | |
| Relevant Assertions: | AS07.05 |
| Relevant Test Requirements: | TE07.05.01-.02 |
| Relevant Vendor Requirements: | VE07.05.01 |
| CRITERIA | LEVEL |
|---|---|
| Trusted Computer Systems Evaluation Criteria (TCSEC) | C2 |
| Canadian Trusted Computer Product Evaluation Criteria (CTCPEC) | C2 Functionality Profile (Functionality Level) T1 (Assurance Criteria Level) |
| Information Technology Security Evaluation Criteria (ITSEC) | F-C2 (Functionality Level) E2 (Assurance Level) |
An O/S can be considered as "evaluated" if it appears on the appropriate Evaluated Products List (EPL) from any one of the following countries: United States, Canada, United Kingdom, Germany, France, and The Netherlands. EPLs can be obtained as follows:
| NATION | ORGANIZATION | CONTACT |
|---|---|---|
| United States (TCSEC) |
National Security Agency INFOSEC Awareness Group Maryland, USA |
TEL: (410) 766-8729 |
| Canada (CTCPEC) |
Communications Security Establishment ATTN: ITS Publications Administrator P.O. Box 9703, Terminal Ottawa, Canada K1G 3Z4 |
TEL: (613) 991-7409 FAX: (613) 991-7411 EMAIL: criteria@cse.dnd.ca |
| United Kingdom (ITSEC) |
Certification Body Secretary UK IT Security and Certification Scheme P.O. Box 152 Cheltenham GL52 5UF, UK |
TEL: +44 1242-238739 FAX: +44 1242-235233 EMAIL: cbsec@itsec.gov.uk |
| Germany (ITSEC) |
Bundesamt fuer Sicherheit in der Informationstechnik Referat II2/II3 Postfach 20 03 63 D-53133 Bonn, Germany |
TEL: +49 228-9582-111 FAX: +49 228-9582-455 EMAIL: zerti@bsi.de |
| France (ITSEC) |
Service Central de la Securite des Systemes d'Information Centre de Certification de la Securite des TI 18 rue du docteur Zamenhof 92131 Issy les Moulineaux, France |
TEL: +33 1-41463753 FAX: +33 1-41463701 EMAIL: 100565.1335@compuserve.com |
| The Netherlands (ITSEC) |
Netherlands National Communications Security Agency P.O. Box 20061 2500 EB The Hague, The Netherlands |
TEL: +31 70-3485637 FAX: +31 70-3486503 EMAIL: criteria@nlncsa.minbuza.nl |